A 10-MHz Multi-bit MASH Delta-Sigma Modulator with Analog Summing Interstage

This paper presents an improved 4-bit twostage Multi-stAge noise Shaping (MASH) delta-sigma modulator (DSM). The two-stage MASH DSM utilizes the second-order chain of Cascade of Integrators with Feedforward (CIFF) and the Cascade of Integrators with distributed Feedback (CIFB) architectures for the first and second stages, respectively. The 4-bit CIFF requires an active adder, which is conventionally implemented with a high-bandwidth high-swing amplifier. In the proposed DSM, the active adder is eliminated and the adder-less integrator is applied in the first stage of the MASH DSM. The first stage quantization noise, which is fed to the second stage, is conventionally extracted from the analog input and digital output of the quantizer in the first stage. The number of quantizer digital output paths increases exponentially with the quantization bit number. A large number of DAC feedback paths in the interstage is avoided by proposing a new interstage topology based on analog summing to derive the first stage quantization noise in the analog domain. The prototype DSM is fabricated in a 0.11μm CMOS process. When operating from a 1.2-V supply, the modulator achieves 67.8-dB peak SNDR, while consuming 25 mW, with an OSR of 8 at a 160-MHz sampling frequency. This research was supported in part by the MSIP(Ministry of Science, ICT and Future Planning), Korea, under the ITRC(Information Technology Research Center)support program(NIPA-2014-H0301-14-1007) supervised by the NIPA(National IT Industry Promotion Agency) and supported in part by Basic Science Research Program through the National Research Foundation of Korea(NRF) funded by the Ministry of Education(2013R1A1A2011973). The authors are with the Department of Electrical Engineering, Hanyang University, Ansan 426-791, Korea E-mail: [email protected].